Modulator-demodulator device capable of detecting an unsynchronized frame state

ABSTRACT

In a modulator-demodulator device, in the transmitter side an error control coding unit is provided for adding redundancy according to a predetermined procedure to a bit sequence to be transmitted from bit processing unit to code the bit sequence. A data sequence-to-coordinate transforming unit transforms the bit sequence from the error control coding unit into a coordinate of a signal point on a complex plane. A coordinate rotating unit rotates the transformed signal point coordinates based on the frame phase information from a frame phase generating unit. In the receiver side, a coordinate rotating unit applies the rotation in the reverse direction of that of the coordinate rotating unit of the transmitter side based on the frame phase information from the frame phase generating unit. A the second unit determines the maximum likelihood signal point by utilizing the redundancy added by the error control coding unit of the transmitter side and corrects the coordinate error of the received signal point. An unsynchronized frame state determining unit determines the unsynchronized frame state based on the distance between the decision point determined by the maximum likelihood signal point determining unit and the demodulated received signal point on the complex plane, whereby the synchronized frame state is quickly detected. In the modulator-demodulator device, an evaluation value is designated for each of the transition sequence of signals. In the receiver side, an error control signal decoding is carried out in the manner that the transition sequence of the maximum likelihood received signal is selected based on the updated evaluation value and the error in the demodulated signal is corrected, whereby the error in the data transmission is corrected.

BACKGROUND OF THE INVENTION Technical Field

The present invention relates to a modulator-demodulator (modem) devicefor a phase modem system, a quadrature amplitude modem system, and thelike. The present invention relates particularly to a device capable ofdetecting an unsynchronized frame state in synchronization transmissionin a modem device. The device according to the present invention isused, for example, for a modem in terminal devices for datacommunication.

Description of Related Art

In a synchronization type data transmission system adopting a phasemodem system, a quadrature amplitude modem system, and the like, framesynchronization between the transmitter side and the receiver side isestablished by introducing a frame synchronization signal in a trainingsignal for the automatic pulling-in of the automatic equalizer of thereceiver side prior to the transmission of the data, and during the datatransmission, the operation is carried out with synchronized frame phasewhich is established during the receiving of the training signal. If theframe phase deviates due to a variation in the characteristics of thedata transmitting network, and an unsynchronized frame state occurs,normal data transmission is prevented, however, this unsynchronizedframe state can be detected only by an abnormal condition of receiveddata. Thus, it would be desirable if a system in which the framesynchronization is detected quickly and reliably could be realized.

In general, for a transmission device which uses an analog line having atransmission rate of 2400 bps to 19200 bps, data transmission speed isnormally set to an integer number times 2400 bps. Thus, in atransmission device in which the modulation speed as an interval forsynchronizing data and for transmitting and receiving synchronized datais different from 2400 bps, and the bit number of the transmission whichis able to be at one time is an integer, it is necessary to carry outtransmission processing in a frame synchronized condition between atransmitter and receiver by using frame phase information in order tocoincide with the transmission speed of an integer multiple of thestandard 2400 bps.

In a prior art system, the frame phase synchronization between atransmitter side and a receiver side is established by introducing aframe synchronization signal in a training signal prior to datatransmission in order to make the frame phase of the receiver sidecoincide with the frame phase of the transmitter side, and during thedata transmission, the operation is carried out with synchronized framephase when the training signal is received.

For example, if one frame is assumed to be constituted by 8 modulations,a modulation synchronization signal is derived by demodulating eachinstance of modulation, frame phase information is generated by countingthe number of these demodulate synchronization signals, and the timingof clearing a counter is preliminarily determined by the frame phasesynchronization signal when the training signal is received, and framephase synchronization between the transmitter side and the receiver sidecan be established even if the frame synchronization signal is notreceived during the data transmission.

However, in such a prior art frame synchronization system, if part ofthe modulation signal within one frame is lost due to a variation in thecharacteristics of the transmitter, such as distortion of the signalwaveform caused by noise during the data transmission, a momentary lossof signal caused by a cut of the line, or the like, the frame phase onthe receiver side deviates and an unsynchronized frame state occurs.Once the unsynchronized frame state occurs, frame synchronization cannotbe recovered, normal data transmission is prevented, and thisunsynchronized frame state can only be detected by the abnormal state ofthe received data, which causes a problem in operation.

SUMMARY OF THE INVENTION

It is the main object of the present invention to provide a device forcausing a rotation of the signal point coordinates on a complex planewhich is a bit sequence from the error control coding means in thetransmitter side transformed based on the frame phase information,causing a rotation of the received signal point coordinates in thereceiver side in the reverse direction of that of the above mentionedcoordinate rotation based on the frame phase information, deciding themaximum likelihood signal point by utilizing the redundancy added by anerror control coding means at the transmitter side, deciding theunsynchronized frame state based on the distance between the decisionpoint decided by the maximum likelihood signal point deciding means anda demodulated received signal point, and thus, to quickly detect theunsynchronized frame state and enhance the reliability of operation of amodem.

In accordance with the present invention, there is provided amodulator-demodulator device capable of detecting an unsynchronizedframe state, characterized in that the device comprises in thetransmitter side: bit processing means for delivering at predeterminedintervals a bit sequence of data to be transmitted; frame phasegenerating means for generating frame phase information in which aninterval of integer N times the interval of the bit sequence constitutesone frame; error control coding means for adding redundancy according toa predetermined procedure to a bit sequence to be transmitted from thebit processing means and coding the bit sequence; data sequence tocoordinate transforming means for transforming the bit sequence from theerror control coding means into coordinates of a signal point on acomplex plane; coordinate rotating means for rotating the transformedcoordinates of a signal point based on the frame phase information fromthe frame phase generating means; and modulation means forphase-modulating or quadrature-modulating the output of the coordinaterotating means and delivering the modulated output to a communicationnetwork. The device comprises in the receiver side: demodulation meansfor demodulating the coordinates of the received signal point on thecomplex plane for the signal from the network; frame phase detectingmeans for detecting the frame synchronization signal from a trainingsignal transmitted from the transmitter side and causing a coincidencebetween the frame phase from the frame phase generating means and thereceived frame phase; coordinate rotating means for applying rotation inthe reverse direction to that of the coordinate rotating means of thetransmitter side; maximum likelihood signal point deciding means fordeciding the maximum likelihood signal point by utilizing the redundancyadded by the error control coding means of the transmitter side andcorrecting coordinate errors of the received signal point; andunsynchronized frame state deciding means for deciding theunsynchronized frame state based on the distance between the decisionpoint by the maximum likelihood signal point deciding means and thedemodulated received signal point on the complex plane.

Also, in accordance with the present invention there is provided amodulator-demodulator device capable of detecting an unsynchronizedframe state, characterized in that a receiver device, connected to anetwork in which data to be transmitted is maximum likelihood coded, thecoded data is phase modulated, and the phase modulated coded data istransmitted. The device comprises: demodulator means for demodulatingthe phase modulated data; compensating means for compensating for signaldeterioration in the rotation of the demodulated base band signal;proximate signal point deciding means for deciding one signal point inthe proximity of the compensated signal from a plurality of ideal signalpoints to be transmitted with respect to the compensated signaldelivered from the compensating means; maximum likelihood signal pointdeciding means for decoding the maximum likelihood coded data, decidingthe maximum likelihood coded data by using a compensation signaldelivered from the compensating means, and delivering the result of thedecision; means for comparing the compensated signal and a hard decisionsignal point delivered by the proximate signal point deciding means andderiving a first error; means for comparing the compensated signal andthe maximum likelihood signal point delivered by the maximum likelihoodsignal point deciding means and deriving a second error; and means forderiving the difference between the first error and the second error;the unsynchronized frame state being detected based on the deriveddifference.

Further, in accordance with the present invention, there is provided amodulator-demodulator device capable of detecting an unsynchronizedframe state, characterized in that the device comprises in thetransmitter side: error control coding means for coding the signal to betransmitted in accordance with a predetermined transition rule forrestricting the transition of signal point on the complex plane;modulation means for modulating the coded signal coded by the errorcontrol coding means to transmit the modulated signal to a communicationnetwork; first transmission signal selecting means for transmitting anon-coded signal not coded by the error control coding means during apredetermined time period upon the start of transmission of thenon-coded signal by the error control coding means; second transmissionsignal selecting means for transmitting a predetermined coded signalcoded by the error control coding means during a predetermined timeperiod upon the completion of the transmission of the non-coded signal,and switching to the transmission of the transmission data upon thecompletion of the transmission of the coded signal; and the devicecomprises in the receiver side: demodulation means for demodulating thesignal point on the complex plane the signal received from thecommunication network; error control signal decoding means for settingan evaluation value for each of the transition sequence of a pluralityof the received signals based on the transition rule of the transmitterside, updating the evaluation value for each receipt of the signals, andselecting the transition sequence of the maximum likelihood receivedsignal based on the updated evaluation value to correct the error in thedemodulated signal point; and evaluation value setting means for settingto said error control signal decoding means the initial value of theevaluation value updated by the coding signal which is first receivedupon the switching from the transmission of the non-coded signal to thetransmission of the coded signal.

BRIEF DESCRIPTION OF THE DRAWING

FIG. 1 shows a modulator-demodulator device according to an embodimentof the present invention;

FIG. 2 shows waveforms of signals for explaining the operation of thedevice shown in FIG. 1;

FIG. 3 shows an arrangement of signal points in Trellis codingmodulation;

FIG. 4 shows a modulator-demodulator device according to anotherembodiment of the present invention; and

FIG. 5 shows waveforms of signals for explaining the operation of thedevice shown in FIG. 4.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

A modulator-demodulator (modem) device according to an embodiment of thepresent invention is shown in FIG. 1.

The operation of the modem shown in FIG. 1 is illustrated in FIG. 2 andFIG. 3.

In the modem of FIG. 1, in the transmitter side, the signal to betransmitted is rotated on a complex plane based on the frame phase, andin the receiver side, the received signal point is rotated on a complexplane in the reverse direction of that of the transmitter side to bereturned to the original position. The unsynchronized frame state isthen decided based on the difference between the distance of harddecision and the distance of soft decision. In a network where theunsynchronized state does not occur frequently, the hard decision signalpoint and the soft decision signal are usually the same point, and, insuch a case, the unsynchronized state is determined and detected by thefact that the difference between the errors of these two points is zero,and that the difference between the errors of these two points willincrease when an unsynchronized state occurs. Therefore, the differencebetween the hard decision value and the receiving signal, i.e., thefirst error, and the difference between the soft decision value and thereceiving signal, i.e., the second error are calculated, the differencebetween the first error and the second error is obtained by, forexample, subtraction, the obtained value is subject to an integrationoperation, or the like to determine a mean value, and then theunsynchronized frame state can be decided when the mean value is morethan a predetermined value.

In the device of FIG. 1, the transmitter side 1 includes a bitprocessing circuit 10 for delivering the bit sequence of thetransmission data at predetermined intervals, a frame phase generatingcircuit 12 for generating frame phase information in which an intervalwhich is an integer multiple of the interval of the bit sequenceconstitutes one frame, a training signal generating circuit 14 forgenerating a training signal including a frame synchronization signalprior to the data transmission, a Trellis coding circuit 16 as the errorcontrol coding circuit for adding redundancy according to apredetermined procedure to the bit sequence to be transmitted from thebit processing circuit 10 and coding the bit sequence, a data sequenceto coordinate transforming circuit 18 for transforming the bit sequencefrom the error control coding circuit 16 into the coordinates of asignal point on the complex plane, a coordinate rotating circuit 20 forrotating the transformed coordinates of the signal point transformed bythe data sequence to coordinate transforming circuit 18 based on theframe phase information from the frame phase generating circuit 12, andmodulation means 24 for phase-modulating or quadrature-modulating theoutput of the coordinate rotating circuit 20 and delivering themodulated output to the communication network 6.

The receiver side 2 includes a demodulation circuit 26 for demodulatingthe coordinates of the received signal point on the complex plane forthe signal from the communication network 6, a frame phase detectingcircuit 32 for controlling the delay amount τ of the variable delaycircuit 30 to cause coincidence between the frame phase from the framephase generating circuit 28 and the received frame phase from thevariable delay circuit 30, a coordinate rotating circuit 34 for applyingrotation in the reverse direction of that of the coordinate rotation inthe transmitter side based on the frame phase information of the framephase generating circuit 28, a first decision circuit 36 for decidingthe nearest signal point among the signal points on the complex planehaving the possibility of transmission with respect to the signalreceiving point coordinates delivered from the coordinate rotatingcircuit 34 as the hard decision, a second decision circuit 38 fordeciding the maximum likelihood signal point by utilizing the redundancyadded by the error control coding means 16 of the transmitter side andcorrecting the coordinate error of the received signal point, and anunsynchronized frame state deciding circuit 5 for deciding theunsynchronized frame state based on the distance between the decisionpoint by the first and/or the second decision circuit 36, 38 and themodulated received signal point on the complex plane.

The unsynchronized frame state decision circuit 5 decides theunsynchronized frame state based on the difference between the distancebetween a point decided by the first decision circuit 36 and thedemodulated receiving point, and the distance between a point decided bythe second decision circuit 38 and the demodulated receiving point.

Concretely, the unsynchronized frame state decision circuit 5 calculatesthe distance between the decision point of the first decision circuit 36and the demodulated receiving point as a first decision error E1 as thehard decision error, calculates the distance between the decision pointof the second decision circuit 38 and the demodulated receiving point asa second decision error as the soft decision error E2, and decides theunsynchronized frame state when the mean value of the differencesbetween the first decision error E1 and the second decision error E2,"E1-E2", becomes more than a predetermined threshold value.

Each of the frame phase generating circuits 12 and 32 generates, asshown in FIG. 2, frame phase information for dividing one frame into thefirst half frame and the latter half frame. The coordinate rotatingcircuit 20 of the transmitter side causes a predetermined coordinaterotation of the signal point coordinates included in the first halfframe, leaving the signal point coordinates included in the latter halfframe not rotated. The coordinate rotating circuit 30 of the receiverside causes a predetermined coordinate rotation of the receiving pointcoordinates included in the first half frame in the reverse direction ofthat of the transmitter side, leaving the receiving point coordinateincluded in the latter half frame not rotated.

The relation between coordinate rotation and non-rotation in the firsthalf frame and the latter half frame is not limited to the abovedescribed relation, but conversely, the first half frame can be ofnon-rotation and the latter half frame can be of rotation.

Further, each of the frame phase generating circuits 12 and 32respectively provided in the transmitter side and the receiver sidegenerates the same frame phase information independently andasynchronously.

In the device shown in FIG. 1, reference numeral 1 denotes thetransmitter side, 2 denotes the receiver side, and the transmitter side1 and the receiver side 2 are connected to each other via thecommunication network 6. The device of FIG. 1 carries out datatransmission at a transmission speed of 14400 bps.

In the transmitter side 1, the bit processing circuit 10 receives thetransmission data from the appropriate terminal. The bit processingcircuit 10 divides the bit sequence of the transmission data into eachmodulation bit, carries out processing such as scrambling or the like,and delivers the scrambled data. Since the transmission speed of thedevice of FIG. 1 is 14400 bps, 14400 bps divided by 2400 bps gives 6bits. That is, the bit processing circuit 10 outputs a bit sequence of 6bits per modulation "Q6n Q5n Q4n Q3n Q2n Q1n".

The bit sequence of 6 bits is supplied from the bit processing circuit10 to the Trellis coding circuit 16 as the error control coding circuit,and the Trellis coding circuit 16 delivers a bit sequence of 7 bitsincluding one bit of redundancy in accordance with a predetermined rule.In this case, the Trellis coding circuit 16 inputs a lower 2 bits "Q2nQ1n" of the bit sequence from the bit sequence processing circuit 10into the coding circuit including a differential coder and a convolutioncoder, and generates a subset of 3 bits "Y2n Y1n Y0n". The 3-bit subsetis combined with the upper 4 bits, and the bit sequence of 7 bits "Q6nQ5n Q4n Q3n Y2n Y1n Y0n" is generated.

The output of the Trellis coding circuit 16 is supplied to the datasequence to coordinate transforming circuit 18 through the switchingcircuit 42. The switching circuit 42 switches the outputs of the Trelliscoding circuit 16 and the training signal generating circuit 14. Namely,the switching circuit 42 selects the training signal from the trainingsignal generating circuit 14 prior to the data transmission, and causesthe pulling-in of the automatic equalizer of the receiver side 2 by thetraining signal from the training signal generating circuit 14.

In the device of FIG. 1, the frame synchronization signal is included inthe training signal generated in the training signal generating circuit14. This frame synchronization signal is detected from the trainingsignals in the receiver side, and the frame synchronization control iscarried out during a training time. Needless to say, the switchingcircuit 42 selects the output of the Trellis coding circuit 16 duringthe data transmission.

The data sequence to coordinate transforming circuit 18 transforms thebit sequence of 7 bits obtained from the Trellis coding circuit 16 tothe coordinates representing the signal point on the complex plane. Forexample, the data sequence to coordinate transforming circuit 18delivers the coordinate value of the signal point on the complex plane,indicated by a black point in FIG. 3, having a binary number of the bitsequence of 7 bits arranged according to the arrangement of signalpoints in Trellis coding modulation shown in FIG. 3, i.e., thecoordinate data constituted by the real number axis (Re) amplitude andthe imaginary number axis (Im) amplitude. In the signal pointarrangement shown in FIG. 3, A, B, C, and D are the signal points forlow speed in the first half portion of the training signal.

Following the data sequence to coordinate transforming circuit 18, thecoordinate rotating circuit 20 is provided for applying a predeterminedrotation to the signal point coordinate on the complex plane from thedata sequence to coordinate transforming circuit 18 based on the framephase information from the frame phase generating circuit 12.

The frame phase generating circuit 12 is actuated when the power supplyis turned on and independently operated for dividing, one frameconstituting 8 modulations into the first half frame and the latter halfframe, as shown in frame phase information of transmitter side (FIG. 2(2)).

According to the frame phase information from the frame phase generatingcircuit 12, the coordinate rotating circuit 20 applies the rotation 0 onthe complex plane, for example the rotation of θ of +90°, for examplethe clockwise rotation of 90° on the complex plane shown in FIG. 3, tothe signal point coordinates from the data sequence to coordinatetransforming circuit 18 included in the first half frame A, leaving thelower signal coordinate included in the latter half frame not rotated,and repeats the same operation for each frame.

The output of the coordinate rotating circuit 20 is supplied to themodulation circuit 24, modulated by phase-modulation, quadraturemodulation, or the like, and the modulated output is delivered to thecommunication network. In other words, in the modulation circuit 24, thereal number axis (Re) amplitude of the signal point coordinatesdelivered from the coordinate rotating circuit 20 is modulated by sinωt,the imaginary number axis (Im) amplitude of the signal point coordinateis modulated by 90° advanced sinωt, and after both components arecomposed together, the composed data is delivered to the communicationnetwork 6.

In the receiver side, reference number 26 indicates a demodulationcircuit for demodulating the receiving point coordinates, i.e., thesignal point coordinates from the signal received from the communicationnetwork 6. In other words, the real number axis (Re) amplitude isdecided by detecting the synchronization of the received signal bycosωt, and the imaginary number axis (Im) amplitude is decided bydetecting the synchronization by sinωt. The demodulation circuit 26includes, of course, a circuit for eliminating the network deteriorationfactor, such as an automatic equalizer, CAPC, and the like.

Following the modulation circuit 26, the frame phase generating circuit28, the variable delay circuit 30 and the frame phase detecting circuit32 are provided for carrying out synchronization control of the framephase.

The frame phase detecting circuit 32 detects the frame synchronizationsignal included in the training signal from the transmitter side 1, andadjusts the delay amount τ of the variable delay circuit 30 so that theframe phase information from the frame phase generating circuit 28 ofthe receiver side 2 is coincident with the phase of the frame phaseinformation of the transmitter side of the frame phase generatingcircuit 12 in the transmitter side.

Both the frame phase generating circuit 12 of the transmitter side andthe frame phase generating circuit 28 of the receiver side anindependently actuated when the device is powered up for generating theframe phase information of the frame divided into the first half frameand the latter half frame, however, the coincidence between the framephases of the transmitter side and the receiver side is not established.In the frame phase detecting circuit 32, the frame phase of thetransmitter side is decided by the frame synchronization signal detectedfrom the training signals, the error of the frame phase of the receiverside in relation to the frame phase of the transmitter side, i.e., thedelay amount τ, is obtained, and the delay amount of the variable delaycircuit 30 is adjusted accordingly. According to the signal delay by thevariable delay circuit 30, the frame phases of the frame phasegenerating circuits 12 and 28 of the transmitter side and the receiverside may made coincident with each other.

The coordinate rotating circuit 34 applies rotation in the reversedirection of that of the transmitter side on the complex plane to thereceiving point coordinate obtained through the variable delay circuit30 based on the frame phase information from the frame phase generatingcircuit 28.

In the device of FIG. 1, in the transmitter side, the coordinaterotating circuit 20 of the transmitter side applies the rotation of, forexample, θ of, for example, +90° for the first half frame, leaving thelatter half frame not being rotated, thus the coordinate rotatingcircuit 34 applies the rotation θ, i.e., -90° as θ, in the reversedirection of that of the transmitter side, to the receiving pointcoordinates included in the first half frame based on the frame phaseinformation from the frame phase generating circuit 28, leaving thelatter half frame not rotated.

Therefore, the signal point coordinates rotated by the coordinaterotating circuit 34 in the transmitter side returns to the initialsignal point coordinates before being rotated in the receiver side,provided that the frame synchronization is properly established.

The receiving point coordinates from the coordinate rotating circuit 34are delivered to each of the first decision circuit 36 as the harddecision means and the second decision circuit 38 as the soft decisionmeans.

The first decision circuit 36 decides the nearest signal point among thesignal points on the complex plane having the possibility oftransmission, and delivers the coordinate point closest to the receivedsignal point as the decision point.

The second decision circuit 38 decides the maximum likelihood signalpoint on the complex plane preliminarily determined by utilizing theredundancy bit according to the Trellis coding performed by the Trelliscoding circuit 16 of the transmitter side, and corrects the error of thereceived signal point. For example, the second decision circuit 38 setsthe evaluation value for each of the transition sequence of a pluralityof the received signals based on the transition rule in accordance withthe Trellis coding in the transmitter side, updates the evaluation valuefor each receipt of the signals, and selects the transition sequence ofthe maximum likelihood received signal based on the updated evaluationnumeral to correct the error in the demodulated signal point. Thisoperation is referred to as a Viterbi decoding decision. For anexplanation of Viterbi decoding decision, refer to, for example, "TheViterbi Algorithm", Proceedings of the IEEE, Vol. 61, No. 3, Pages268-278, published by I.E.E.E., U.S.A., March 1973.

The signal point decided by the second decision circuit 38 is deliveredto the coordinate to data sequence transforming circuit 44, and thecoordinate to data sequence transforming circuit 44 is provided with themapping circuit having binary numbers of the 6-bit data for each ofsignal point arrangements. The decision coordinate point is transformedinto 6-bit data, and the transformed data is delivered to a bitprocessing circuit 46. The bit processing circuit 46 carries outdescrambling and the like, combines the 6-bit data, and delivers thereceived data to the terminal.

Further, in the device of FIG. 1, the unsynchronized frame statedecision circuit 5 is provided. For the unsynchronized frame statedecision circuit 5, the demodulated receiving point from the coordinaterotating circuit 34, the hard decision point from the first decisioncircuit 36, and the soft decision point from the second decision circuit38 are delivered.

The unsynchronized frame state decision circuit 5 is constituted byerror calculating circuits 50 and 52, difference calculating circuit 54,mean value determining circuit 56, and decision circuit 58.

The error calculating circuit 50 calculates the distance on the complexplane between the demodulated receiving point and the decision point ofthe first decision circuit 36 to derive a hard decision error E1.

The error calculating circuit 52 calculates the distance on the complexplane between the demodulated receiving point and the soft decisionpoint of the second decision circuit 36 to derive a soft decision errorE2.

The hard decision error E1 calculated by the error calculating circuit50 and the soft decision error E2 calculated by the error calculatingcircuit 52 are delivered to the difference calculating circuit 54, andthe difference between the decision errors "E2-E1" is calculated in thedifference calculating circuit 54. The output of the differencecalculating circuit 54 is supplied to the mean value determining circuit56. The mean value determining circuit 56 determines the mean differencevalue between, for example, several frames. Finally, the decisioncircuit 58 compares the determined mean value with a predeterminedthreshold value, and generates an output decision of an unsynchronizedframe state when the mean value becomes more than the predeterminedthreshold value.

Next, the operation of the device of FIG. 1 will be described referringto the signal waveforms shown in FIG. 2.

When the power is switched on in the transmitter side 1 and the receiverside 2, the frame phase generating circuit 12 of the transmitter side 1and the frame phase detecting circuit 32 of the receiver side 2 areindependently actuated, and generate frame phase information indicatingthe first half frame and the latter half frame independently (FIGS. 2(2) and (6)).

The switch circuit 42 is switched to the training signal 14 side, andthe training signal including the frame synchronization signal istransmitted from the training signal generating circuit 14 to thereceiver side 2. The receiver side 2, upon the receipt of the trainingsignal from the transmitter side 1, carries out the network compensationprocessing including the pulling-in of the automatic equalizer providedin the demodulation circuit 26 and the like, detects the framesynchronization signal included in the training signal by the framephase detecting circuit 32, and detects the timing of the frame phase ofthe frame phase generating circuit 12 of the transmitter side 1. Thus,in the frame phase detecting circuit 32, the phase error between theframe phase information of the transmitter side and the frame phaseinformation of the receiver side, i.e., the delay amount τ, is detected,and the frame phase detecting circuit 32 adjusts the delay amount of thevariable delay circuit 30 to the detected delay amount τ. Accordingly,even if the coincidence between the frame phases of the transmitter sideand the receive side is not established, the frame of the receivedsignal obtained through the signal delay of the variable delay circuit30 becomes coincident with the frame phase information of the framephase generating circuit 28 by setting the delay amount τ of thevariable delay circuit 30 based on the frame synchronization signal.

Upon the completion of transmission of the training signal, thetransmitter side 1 starts the transmission of data from the terminal.

In the bit processing circuit 10, the bit sequence of 6 bits permodulation is derived from the transmission data synchronously with themodulation synchronization signal, a single redundancy 1 bit is added tothe 6 bit sequence by coding the lower 2 bits in the Trellis codingcircuit 16 to transform the 6 bit sequence to a 7 bit sequence, and thetransformed bit sequence is delivered to the data sequence to coordinatetransforming circuit 18 through the switch circuit 42. An example of thesignal point arrangement in the Trellis coding modulation is shown inFIG. 4. The data sequence to coordinate transforming circuit 18transforms the 7 bit sequence to the signal point coordinates by amapping circuit having a signal point arrangement corresponding to thebinary numbers of the 7 bit sequence delivered from the Trellis codingcircuit, and delivers the transformed data to the coordinate rotatingcircuit 20.

Frame phase information is supplied from the frame phase generatingcircuit 12 to the coordinate rotating circuit 20, and the coordinaterotating circuit 20 causes a predetermined coordinate rotation θ of, forexample, +90° as θ on the complex plane, of 4 signal point coordinatesincluded in the first half frame of the frame phase information, leavingthe 4 signal coordinates included in the latter half frame not rotated,and delivers the signal point coordinates to the modulation circuit 24.Thus, the signal point coordinates successively delivered through thecoordinate rotating circuit 20 are modulated in the modulation circuit24, and the modulated signal point coordinates are delivered to thecommunication network 6. In this case, the real number axis (Re)coordinate value is modulated by cosωt, while, the imaginary number axis(Im) coordinate value is modulated by 90° advanced sinωt, and thesynthetic signal of both components is delivered to the communicationnetwork.

In the receiver side 2, the signal point coordinates are demodulatedfrom the received signal from the communication network 6 by thedemodulation circuit 26, the variable delay circuit 30 applies thesignal delay of delay amount τ, which is set while receiving thetraining signal, to the demodulated signal point coordinates so that thesignal point coordinates as synchronized with the frame phase anddelivered to the coordinate rotating circuit 34. Based on the phaseinformation from the frame phase generating circuit 28, i.e., the framephase information (FIG. 2 (6)), the coordinate rotating circuit 34causes the coordinate rotation θ, for example θ=-90°, in the reversedirection of that of the transmitter side for the receiving pointcoordinates of the first half frame of one frame, leaving the latterhalf frame thereof not rotated. Thus, the receiving point delivered fromthe coordinate rotating circuit 34 returns to the original signal pointbefore being rotated in the transmitter side.

The receiving point coordinates rotated by the coordinate rotatingcircuit 34 are delivered to the second decision circuit 38. The seconddecision circuit 38 corrects the error of the demodulated receivingpoint by deciding the maximum likelihood signal point on the complexplane according to the Viterbi decoding processing, the coordinate todata sequence transforming circuit 44 transforms the error-correctedreceived signal point to 6 bit data using the mapping circuit, the bitprocessing circuit 46 carries out processing such as de-scrambling andthe like on the 6 bit data, then after that, combines the 6 bit data ofeach successive modulation, and transmits the combined data to theappropriate terminal side.

In the unsynchronized frame state decision circuit 5, the errorcalculating circuits 50 and 52 calculate the hard decision error E1 andthe soft decision error E2 by using the decision point obtained from thefirst decision circuit 36 and the second decision circuit 38 at each ofthe received modulation signal of one modulation, the differenceoperation circuit 54 finds the difference between the errors, the meanvalue determining circuit 56 determines the mean value with respect to apredetermined number of frames, and compares the result withpredetermined threshold value which is set in the second decisioncircuit 58.

One or more modulation signals may be missing due to an instantaneousinterruption caused by switching a connection or the like on thecommunication network 6 during data transmission between the transmitterside 1 and the receiver side 2. In this case, the number of themodulation synchronization signal (FIG. 2 (8)) becomes 7 or less in oneframe interval, and the frame phase of the receiver side is deviated.When the frame phase of the receiver side is deviated, the modulationsignal included in the rotated frame of the transmitter side does notcorrespond to the timing of the frame of reverse rotation in thereceiver side but corresponds to the non-rotated frame, or in thetransmitter side, the modulation signal included in the non-rotatedframe corresponds to the frame of reverse rotation in the receiver side.Accordingly, even if the coordinate rotating circuit 34 of the receiverside 2 applies the reverse rotation to the transmitter side, the signalpoint does not return to its initial position. Thus, when the framephase is deviated, the continuity of the demodulated receiving point isdestroyed and a significant soft decision error E2 is caused withrespect to the decision point of the second decision circuit 38. Sincelost frame synchronization cannot be recovered, the mean value of themean value determining circuit 56 becomes more than the threshold valueof the second decision circuit 58. Thus, the output of decision of anunsynchronized frame state can be obtained.

If the decision output of the unsynchronized frame state decisioncircuit 5 is obtained, the system is in a state in which datatransmission is impossible. In that case, the normal data transmissioncan be restored by restarting both the transmitter side and the receiverside, and commencing again the transmission of the training signal.

Further, in the unsynchronized frame state decision circuit 5, theunsynchronized frame state is decided based on the mean value of thehard decision error E1 and the soft decision error E2, and accordinglythe unsynchronized frame state can be exactly decided by eliminating theerror caused by the characteristics of the communication network. Inother words, both the hard decision error E1 and the soft decision errorE2 significantly change according to the characteristics of the network,and if the network characteristics are stable, the unsynchronized framestate can be decided only by detecting an increase in the soft decisionerrors due to the unsynchronized frame state.

In the device of FIG. 1, the rotation and reverse rotation are carriedout only for the first half frame of the frame phase information of thetransmitter side. Another way, i.e., non-rotation of the first halfframe and rotation and reverse rotation of the latter half frame, may beused to obtain the same effect.

Also, in the device of FIG. 1, the frame phase information is dividedinto the first half frame and the latter half frame, but other framephase information with frames divided into 3 divisions, 4 divisions, oran other appropriately selected division of frame phase information maybe used.

Further, the device of FIG. 1 is an example in which the rotation of thesignal point coordinates by 90° is carried out on the complex plane, butother rotation angles may be used provided that the rotation angle isappropriately selected so that an adequate soft decision error can beobtained according to the unsynchronized frame state.

The device according to another embodiment of the present invention isshown in FIG. 4. The operation of the device of FIG. 4 is illustrated inFIG. 5.

The device shown in FIG. 4 is technically closely related to the deviceof FIG. 1, and it is preferable to use the technology of the device ofFIG. 1 together with the technology of the device of FIG. 4.

In the device of FIG. 4, the transmitter side 1 and the receiver side 2are connected through the communication network 6 such as a telephonenetwork and the like, user data to be transmitted by the transmitterside 1 is coded for error control, and is then modulated byphase-modulation or quadrature modulation and delivered to thecommunication network 6. In the receiver side 2, the received signalfrom the communication network 6 is demodulated, errors are corrected bythe maximum likelihood signal point decoding, and the transmission data(user data) is reproduced.

First, the transmitter side 1 will be described. In the transmitter side1, a bit processing circuit 300 is provided. The transmission data issupplied from the user transmission terminal to the bit processingcircuit 300, the transmission data is processed by bit processing suchas scrambling or the like, and the transmission data is divided into thenumber of bits to be transmitted for each modulation, and is thendelivered. For example, the bit processing circuit 300 outputs a bitsequence of 6 bits per modulation "Q6n Q5n Q4n Q3n Q2n Q1n", where n isan integer indicating the modulation number.

Reference numeral 180 denotes a selector switch as a second deliverysignal selector means. The selector switch 180 switches the output ofthe bit processing circuit 300 and the output of a high speed signalgenerating circuit 280 to an error control coding circuit (Trellis codecircuit) 110. That is, the selector switch 180 delivers the high speedsignal from the high speed signal generating circuit 280 for apredetermined time period from the start of coding and decoding at thestart stage prior to the transmission of the transmission data, afterthat, switches to the output of the transmission data from the bitprocessing circuit 300.

The Trellis coding circuit 110 as the error control coding means carriesout coding for controlling errors according to a transition rule whichrestricts the transition on the complex plane of the signal point fortransmitting in accordance with a predetermined procedure, with respectto the transmission signal.

To the Trellis code circuit 110, the bit sequence of 6 bits permodulation "Q6n Q5n Q4n Q3n Q2n Q1n" is supplied from the bit processingcircuit 300 via, for example, the selector switch circuit 180. Thesubset "Y2n Y1n Yn" to which the redundancy 1 bit is added by coding thelower 2 bits "Q2n Q1n" of the above mentioned bit sequence by using thedifferential coder and the convolution coder, is produced. The 7 bitsequence including this subset and the upper 4 bits "Q6n Q5n Q4n Q3n",i.e., the bit sequence constituted by 6 bits and 1 added redundancy bitis coded as "Q6n Q5n Q4n Q3n Y2n Y1n Y0n", and this coded signal isdelivered.

The output of the Trellis code circuit 110 is supplied to the bitsequence to coordinate transforming circuit 340, and this bit sequenceto coordinate transforming circuit 340 outputs the signal pointcoordinate on the phase plane as the complex plane corresponding to thetransmission bit sequence.

The signal point coordinate on the complex plane with respect to theinput 7 bit sequence from the Trellis code circuit 110 transformed bythe bit sequence to coordinate transforming circuit 340 is, for example,as shown in FIG. 3.

The output of the bit sequence to coordinate transforming circuit 340 issupplied to the modulation circuit 140 through the selector switchcircuit 160 which is the first delivery signal selector means. Theselector switch circuit 160 switches the output of the bit sequence tocoordinate transforming circuit 340 and the output of the low speedsignal generating circuit 260 which comprise the non-coded signalgenerating circuit to the modulation circuit 140, and at the actuationstage prior to the transmission of the transmission data, the selectorswitch circuit 160 selects the output of the low speed signal generatingcircuit 260, delivers the low speed signal to the communication network6 through the modulation circuit 140 for a predetermined time period,and selects the output of the bit sequence to coordinate transformingcircuit 340, i.e., the signal output coded by the Trellis code circuit110 upon the completion of the delivery of the low speed signal.

The modulation circuit 140 generates the modulation signal correspondingto the coordinate input of the transmission signal point on the complexplane, or more concretely, modulates the rear number axis (Re) amplitudein the signal point input coordinate on the complex plane by amplitudemodulation by cosωt, further modulates the imaginary number axis (Im)amplitude by amplitude modulation by sinωt having a 90° leading phase,combines these components, and delivers these combined data to thecommunication network 6.

In the receiver side 2, reference numeral 200 indicates a demodulationcircuit which demodulates the modulation signal received from thecommunication network 6, and outputs the coordinates of the receivedsignal point on the complex plane. In other words, the real number axis(Re) amplitude component and the imaginary number axis (Im) amplitudecomponent are reproduced by detecting synchronization of the receivedmodulation signal by respective cosωt and sinωt, and the coordinate dataof the received signal point is detected.

The demodulated output from the demodulation circuit 200 i.e., thecoordinate data of the received signal point, is supplied to the errorcontrol signal decoding circuit 220 as the error control decoding means,which corrects the error of the received signal point from thedemodulation circuit 200 by selecting the transition sequence of themaximum likelihood received signal utilizing the transition rule of thesignal point restricted in the transmitter side, and by delivering themaximum likelihood signal point coordinate on the complex planeaccording to the selected transition sequence.

The error control signal demodulation circuit 220, having the evaluationvalue for each of a plurality of the receiving sequences defined by thetransition rule of the signal point restricted by the transmitter side,updates the evaluation value at every receipt of the signal, andcorrects the error of the received signal point by selecting the signalsequence of the maximum likelihood received signal based on the updatedevaluation value.

The coordinate data of the receiving point the error of which iscorrected by the maximum likelihood decoding circuit 220 is supplied tothe coordinate to bit sequence transforming circuit 360. The coordinateto bit sequence transforming circuit 360 delivers the bit sequencecorresponding to the input receiving point coordinates on the complexplane. The device of FIG. 4 is an example of the case in which the bitsequence of 6 bits per modulation is transmitted, thus, the bit sequence"Q6n Q5n Q4n Q3n Q2n Q1n" is delivered from the coordinate to bitsequence transforming circuit 360.

The bit sequence delivered from the coordinate to bit sequencetransforming circuit 360 is supplied to the bit processing circuit 380which joins the bit sequences divided per 1 modulation, carries out thebit processing such as the scrambling and the like on each of bitsequences, and delivers the receiving data to the terminal of thereceiver side.

Further, in the device of FIG. 4, the evaluation value setting circuit240 is provided against the error control signal decoding circuit 220provided in the receiver side. The evaluation value setting circuit 240designates to the error control signal decoding circuit 220 theevaluation value which is updated by the first received high speedsignal when the transmission signal from the transmission side 1 isswitched from a non-coded low speed signal to the coded high speedsignal. For the evaluation value to be designated by the evaluationvalue setting means 240, the evaluation value which represents thetransition sequence of the received signal available for the errorcontrol signal decoding circuit 220 when the number of received codedhigh speed signals delivered from the transmitter side 1 is more than apredetermined number.

The operation of the device of FIG. 4 will be described with referenceto FIG. 5.

When the transmitter side 1 receives the transmission request from theterminal side at the time t1, the selector switch circuit 160 switchesto the low speed signal generating circuit 260 side, the low speedsignal is supplied from the low speed signal generating circuit 260 tothe modulation circuit 140 through the selector switch circuit 160, andthe low speed signal modulated by the modulation circuit 140 isdelivered to the communication network 6. The receiving signal from thecommunication network is demodulated by the demodulation circuit 200,the low speed signal is reproduced, and the actuation of the errorcontrol signal decoding circuit 220 provided in the receiver side 2, thecoordinate to bit sequence transforming circuit 360, the bit processingcircuit 380, and other necessary circuit portions, is carried out. Whenthe actuation operation is carried out upon the reception of a low speedsignal, the decoding operation by the error control signal decodingcircuit 220 is not carried out.

When a predetermined time period from the time t1 has elapsed, i.e.,when the transmission of the low speed signal of a predetermined numbercovering successive data is completed, the selector switch circuit 160cuts off the output of the low speed signal generating circuit 260 andconnects the output of the bit sequence to coordinate transformingcircuit 340 to the modulation circuit 140. At the same time, theselector switch circuit 180 selects the output of the simultaneouslyactuated high speed signal generating circuit 280 at a timing ofcompletion of the low speed signal generating circuit 260, and suppliesthe high speed signal having the bit pattern predetermined for thistransmission system.

The high speed signal generating circuit 280 outputs the bit sequence of6 bits having a predetermined fixed bit pattern, and the bit pattern iseither the repetition of the same pattern or the repetitive output of aplurality bit patterns which change in accordance with a predeterminedprocedure.

The first coded high speed signal is demodulated by the demodulationcircuit 200 in the receiver side 2, and the signal point coordinate datais supplied to the error control signal decoding circuit 220, then thetime period of the low speed signal is measured by a timer (not shown)in the receiver side, and when a predetermined time period is elapsed,the timing of supply of the signal point coordinate data is identified.The error control signal decoding circuit 220 updates the evaluationvalue which is predetermined by the evaluation value setting means 240based on the received and demodulated signal point coordinate at thistiming, and, based on the updated evaluation value, the error of thedemodulated signal point coordinates is corrected so that the signalpoint coordinate in accordance with the transition sequence of thereceiving signal is realized.

When the first coded high speed signal is received, the high speedsignal previously coded is not demodulated in the error control signaldecoding circuit 220, therefore, an evaluation value to be updated doesnot exist in that circuit 220. However, in the device of FIG. 4, inappearance, the same state as the state in which more than apredetermined number of the high speed signals has been received and theerror control signals have been demodulated is established by theevaluation value setting means 240. Therefore, in the device of FIG. 4,the evaluation value of the receiver side is a numeral having continuityfrom the viewpoint of the transition rule of the transmission signal,and reliable correction of the error can be carried out in the errorcontrol signal decoding circuit 220 even immediately after the switchingtransmission of the decoded high speed signals.

The receiving signal point coordinates the error of which is correctedby the error control signal decoding circuit 220, are transformed intothe bit sequence of 6 bits by the coordinate to bit sequencetransforming circuit 360, and after that, are transformed to thereceiving data in which the bit sequence divided at each modulation bythe bit processing circuit 380, and these bit sequences are connected insequence.

When the transmission of the high speed signals is completed at the timet3 after a predetermined time period from the time t2 has elapsed, theselector switch circuit 180 of the transmitter side 1 cuts off theoutput of the high speed signal generating circuit 280, connects theoutput of the bit processing circuit 300 to the error control codingcircuit 110, carries out the bit processing such as the scrambling andthe like on the transmission data, divides the data into 6 bit sequencesat each 1 modulation and delivers them to the error control codingcircuit 110, and in the same way as the high speed signal, causes codingfor controlling errors, and delivers the data to the receiver side 2 sothe correct data can always be received in the receiver side 2 due tothe error correction by the error control signal decoding circuit 220.

Although the device of FIG. 4 is an example of the device in which thedata divided into the bit sequence of 6 bits per modulation istransmitted, the device according to the present invention is notrestricted to this example, and the number of bits per 1 modulation maybe appropriately selected based on the transmission speed.

We claim:
 1. A modulator-demodulator device capable of detecting anunsynchronized frame state in a communication network, said devicecomprising in the transmitter side:bit processing means for delivering,at predetermined intervals, a bit sequence of data to be transmitted;frame phase generating means for generating frame phase informationspecifying that the interval of an integer N times the interval of thebit sequence constitutes one frame; error control coding means foradding redundancy to the bit sequence according to a predeterminedprocedure and for coding the bit sequence to output a coded bitsequence; data sequence-to-coordinate transforming means fortransforming the coded bit sequence into coordinates of a signal pointon a complex plane; transmitter coordinate rotating means for rotatingthe coordinates of a signal point based on the frame phase informationto produce rotated coordinates of a signal point; and modulation meansfor phase-modulating or quadrature-modulating the rotated coordinates ofa signal point, for delivering a modulated signal to the communicationnetwork and for delivering the frame phase information in a trainingsignal to the communication network; and said device comprises in thereceiver side: demodulation means for demodulating the modulated signalfrom the communication network to provide a received signal point on acomplex plane; frame phase detecting means for receiving the frame phaseinformation in a training signal from the communication network fordetecting a phase of the received signal point to provide a receivedframe phase and for adjusting the received signal point to maintaincoincidence between the frame phase information and the received signalpoint to produce an adjusted received signal point; receiver coordinaterotating means for rotating coordinates of the adjusted received signalpoint in a reverse direction of that of said transmitter coordinaterotating means based on the frame phase information to produce rotatedcoordinates of a received signal point; maximum likelihood signal pointdetermining means for determining a maximum likelihood signal point byadding redundancy to the rotated coordinates of a received signal pointlike the redundancy added by said error control coding means of thetransmitter side and by correcting a coordinate error of the rotatedcoordinates of the received signal point; and unsynchronized frame statedetermining means for determining a soft unsynchronized frame statebased on a distance between the maximum likelihood signal point and therotated coordinates of the received signal point.
 2. A device as definedin claim 1,wherein said device further comprises latest signal pointdetermining means for determining a latest signal point by a signalpoint nearest to the rotated coordinates of the received signal point;and wherein said unsynchronized frame state deciding meanscomprisesmeans for determining a hard unsynchronized frame state basedon a distance between the latest signal point and the rotatedcoordinates of the received signal point, and means for determining acombined unsynchronized frame state based on a distance between the softunsynchronized frame state and the hard unsynchronized frame state.
 3. Adevice as defined in claim 2, wherein said unsynchronized frame statedeciding means comprises output means for determining an outputunsynchronized frame state when a mean value of the unsynchronized framestate becomes more than a predetermined threshold value.
 4. A device asdefined in claim 1, wherein each of said frame phase generating meansand said frame phase detecting means comprise means for generatingsimilar frame phase information independently and asynchronously.
 5. Adevice as defined in claim 1,wherein each of said frame phase generatingmeans and said frame phase detecting means comprise means for generatingframe phase information indicating a division of one frame into a firsthalf frame including a first signal point coordinate and a second halfframe including a second signal point coordinate, wherein saidtransmitter coordinate rotating means comprises means for causing asignal point coordinate rotation of the first signal point coordinate ina forward direction and for leaving the second signal point coordinatenot rotated, wherein said receiver coordinate rotating means comprisesmeans for causing a signal point coordinate rotation of the firstreceiving point coordinate in a reverse direction and for leaving thesecond receiving point coordinate not rotated.
 6. A device as defined inclaim 5,wherein said transmitter coordinate rotating means comprisesmeans for maintaining the first signal point coordinate and for causinga signal point coordinate rotation of the second signal point coordinatein a forward direction, and wherein said receiver coordinate rotatingmeans comprises means for maintaining the second signal point coordinateand and for causing a predetermined coordinate rotation of the firstsignal point in a reverse direction.